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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ADS9224R sbas876 ? august 2018 ads92x4r dual, low latency, simultaneous-sampling sar adc 1 1 features 1 ? high resolution, high throughput: ? ADS9224R: 16 bit, 3 msps ? ads9234r: 14 bit, 3 msps ? fast response time with low latency: 333 ns ? higher performance over wide analog bandwidth: ? ADS9224R: 83-db sinad at 1.4 mhz ? ads9234r: 80-db sinad at 1.4 mhz ? two simultaneously sampled channels ? unipolar, fully differential inputs ? wide common-mode voltage range ? excellent dc and ac performance: ? ADS9224R: ? 16-bit nmc dnl, 2-lsb max inl ? 93.5-db snr, ? 110-db thd ? 80-db cmrr ? ads9234r: ? 14-bit nmc dnl, 1-lsb max inl ? 85.6-db snr, ? 106-db thd ? 75-db cmrr ? integrated reference and reference buffers ? integrated refby2 buffer for setting common mode ? integrated data averaging ? enhanced-spi interface for mcus and fpgas: ? wide read cycle to read data with mcus ? crt for data transfers with digital isolators ? ddr modes for fpgas ? parallel byte mode for easy interface ? extended temperature range: ? 40 c to +125 c ? small footprint: 5-mm 5-mm vqfn 2 applications ? optical encoders: incremental and absolute ? sonar receivers ? optical networking: edfa gain control loop ? power quality measurement ? digital power supply ? i/q demodulators ? medical imaging: ct scanners, mri scanners 3 description the ads92x4r is a pin-compatible, high-speed, dual, simultaneous-sampling, analog-to-digital converters (adc) with an integrated reference and reference buffer. the device can operate on a single 5-v supply and supports unipolar, fully differential analog input signals with excellent dc and ac specifications. the device supports spi-compatible serial (enhanced-spi) and byte-wide parallel interfaces, making the device easy to pair with a diversity of microcontrollers, digital signal processors (dsps), and field-programmable gate arrays (fpgas). the device comes in a space-saving, 5-mm 5-mm, vqfn package. the ads92x4r is specified for the extended temperature range of ? 40 c to +125 c. device information (1) part number package body size (nom) ads92x4r vqfn (32) 5.00 mm 5.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. typical application diagram adc adc host reference position encoder sine cosine low latency sar absolute/incremental encoder adc adc i q low latency sar 90 0 local oscillator baseband signal host sonar advance information tools & software technical documents ordernow productfolder support &community
2 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics: ads92x4r ....................... 6 6.6 electrical characteristics: ADS9224R ....................... 7 6.7 electrical characteristics: ads9234r ....................... 8 6.8 timing requirements ................................................ 9 6.9 switching characteristics ........................................ 10 7 detailed description ............................................ 14 7.1 overview ................................................................. 14 7.2 functional block diagram ....................................... 14 7.3 feature description ................................................. 15 7.4 device functional modes ........................................ 19 7.5 ready/strobe output ........................................ 23 7.6 programming ........................................................... 23 7.7 register maps ......................................................... 34 8 application and implementation ........................ 39 8.1 application information ............................................ 39 8.2 typical application .................................................. 41 9 power supply recommendations ...................... 43 10 layout ................................................................... 44 10.1 layout guidelines ................................................. 44 10.2 layout example .................................................... 45 11 device and documentation support ................. 46 11.1 related documentation ......................................... 46 11.2 receiving notification of documentation updates 46 11.3 community resources .......................................... 46 11.4 trademarks ........................................................... 46 11.5 electrostatic discharge caution ............................ 46 11.6 glossary ................................................................ 46 12 mechanical, packaging, and orderable information ........................................................... 46 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes august 2018 * initial release. advance information
3 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions rhb package 5-mm 5-mm, 32-pin vqfn top view pin functions pin function description name no. ainm_a 2 analog input negative analog input for channel a. ainp_a 1 analog input positive analog input for channel a. ainm_b 8 analog input negative analog input for channel b. ainp_b 7 analog input positive analog input for channel b. avdd 12, 29 power supply analog power-supply pin. connect a 1- f decoupling capacitor between pin 12 and pin 11. connect pins 12 and 29 together. connect a 1- f decoupling capacitor between pin 29 and pin 30. convst 13 digital input conversion start input pin. a convst rising edge starts the conversion for adc_a and adc_b. cs 14 digital input chip-select input pin; active low. the device takes control of the data bus when cs is low. the sdo-x pins go to hi-z when cs is high. dvdd 28 power supply interface power-supply pin. connect a 1- f decoupling capacitor between pin 27 and pin 28. gnd 4, 11, 27, 30 power supply ground nc 6 ? no external connection pd/ rst 26 digital input asynchronous reset or power-down input pin. see the reset or power-down section. ready/strobe 25 digital output indicates data ready or strobe output for data capture. advance information 32 refm_a 9 refm_b 1 ainp_a 24 sdo-0/0a 31 refp_a 10 refp_b 2 ainm_a 23 sdo-1/1a 30 gnd 11 gnd 3 refby2 22 sdo-2/2a 29 avdd 12 avdd 4 gnd 21 sdo-3/3a 28 dvdd 13 convst 5 refout 20 sdo-4/0b 27 gnd 14 cs 6 nc 19 sdo-5/1b 26 pd/rst 15 sdi 7 ainp_b 18 sdo-6/2b 25 ready/strobe 16 sclk 8 ainm_b 17 sdo-7/3b not to scale thermal pad
4 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin function description name no. refby2 3 analog output refby2 buffer output. connect a 1- f decoupling capacitor between pin 3 and pin 4. refout 5 analog output internal reference output. connect a 1- f decoupling capacitor between pin 5 and pin 4. refm_a 32 analog output negative output of reference buffer a. negative reference input for adc_a. externally connect to the device gnd. refm_b 9 analog output negative output of reference buffer b. negative reference input for adc_b. externally connect to the device gnd. refp_a 31 analog output positive output of reference buffer a. positive reference input for adc_a. connect a 10- f decoupling capacitor between pin 31 and pin 32. refp_b 10 analog output positive output of reference buffer b. positive reference input for adc_b. connect a 10- f decoupling capacitor between pin 9 and pin 10. sclk 16 digital input clock input pin for the serial interface. sdi 15 digital input serial data input pin. this pin is used to program the device registers. sdo-0/0a 24 digital output spi mode: data output 0 for channel a. parallel byte mode: least significant bit (lsb) from the data byte. sdo-1/1a 23 digital output spi mode: data output 1 for channel a. parallel byte mode: lsb+1 from the data byte. sdo-2/2a 22 digital output spi mode: data output 2 for channel a. parallel byte mode: lsb+2 from the data byte. sdo-3/3a 21 digital output spi mode: data output 3 for channel a. parallel byte mode: lsb+3 from the data byte. sdo-4/0b 20 digital output spi mode: data output 0 for channel b. parallel byte mode: lsb+4 from the data byte. sdo-5/1b 19 digital output spi mode: data output 1 for channel b. parallel byte mode: lsb+5 from the data byte. sdo-6/2b 18 digital output spi mode: data output 2 for channel b. parallel byte mode: lsb+6 from the data byte. sdo-7/3b 17 digital output spi mode: data output 3 for channel b. parallel byte mode: most significant bit (msb) from the data byte. thermal pad pad power supply exposed thermal pad. ti recommends connecting this pin to the printed circuit board (pcb) ground. advance information
5 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit analog supply voltage avdd to gnd ? 0.3 6 v digital supply voltage dvdd to gnd ? 0.3 6 v digital input voltage cs, convst, sdi, sclk, pd/ rst to gnd ? 0.3 dvdd + 0.3 v analog input voltage ainp_a, ainp_b to gnd ? 0.3 avdd + 0.3 v analog input voltage ainm_a, ainm_b to gnd ? 0.3 avdd + 0.3 v input or output current to any pin except power supply pin ? 10 10 ma maximum virtual junction temperature t j 150 c storage temperature t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit avdd analog supply voltage 4.5 5 5.5 v dvdd digital supply voltage operating range 1.65 3.3 5.5 v digital supply voltage for sclk > 20 mhz 2.35 3.3 5.5 v t a ambient temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) ads92x4r unit rhb (vqfn) 32 pins r ja junction-to-ambient thermal resistance 29 c/w r jc(top) junction-to-case (top) thermal resistance 17.1 c/w r jb junction-to-board thermal resistance 9.4 c/w jt junction-to-top characterization parameter 0.2 c/w jb junction-to-board characterization parameter 9.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 0.8 c/w advance information
6 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) ideal input span; does not include gain or offset error. (2) does not include the variation in voltage resulting from solder shift effects. 6.5 electrical characteristics: ads92x4r all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 to 5.5 v and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v parameter test conditions min typ max unit analog input fsr full-scale input voltage (1) v ref = 2.5 v -4.096 4.096 v v in absolute input voltage (ainp or ainm to gnd) v ref = 2.5 v 0 4.096 v v cm common-mode input range v ref = 2.5 v 1.848 2.248 v i in analog input leakage current 1 a c i input capacitance sample mode 16 pf hold mode 1 sampling dynamics t cycle cycle time 333 ns f sample sampling rate 3 msps t acq acquisition time 140 ns t a aperture delay 8 ns t a mismatch 40 ps t jitter aperture jitter 2 ps bw analog input bandwidth -3db input signal 100 mhz -0.1 db input signal 20 mhz voltage reference output v ref (2) refout voltage t a = 25 c 2.498 2.5 2.502 v v ref / t v ref drift 5 20 ppm/ c v ref / avdd v ref line regulation avdd variation 4.5 v to 5.5 v 200 v/v i refout refout output current capability | v ref | < 2 mv 1.5 a c refout refout capacitor for specified performance 1 f t wkup- refout refout wake-up time c refout = 1 f 10 ms internal reference buffer g refbuf reference buffer gain 1.6384 v/v e o-refbuf reference buffer output offset (v refp_x - v ref ) at t a = 25 c 500 v t a = -40 c to 125 c ? 1 0 1 mv e o-refbuf / t reference buffer output offset temperature drift 10 v/ (v refp_a - v refp_b ) reference buffer output mismatch t a = -40 c to 125 c ? 500 50 500 v c refp_x reference buffer output capacitor for specified performance, between each pair of refp and refm 7 10 27 f t refbuf-settle reference buffer output settling time c refp_x = 10 f 25 ms refby2 output v refby2 refby2 uutput voltage en_refby2_offset = 0, v ref = 2.5 v 2.043 2.048 2.053 v en_refby2_offset = 1, v ref = 2.5 v 2.133 2.148 2.163 v i refby2 refby2 output current capability 3 ma refby2 output capacitor 1 f advance information
7 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ads92x4r (continued) all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 to 5.5 v and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v parameter test conditions min typ max unit (3) all specifications expressed in decibels (db) refer to the full-scale input (fsr) and are tested with an input signal 0.5 db below full- scale, unless otherwise specified. refby2 output noise with specified output capacitor 10 v rms digital outputs v oh high level output voltage i oh = 500 a source 0.8 dvdd dvdd v v ol low level output voltage i ol = 500 a sink 0 0.2 dvdd v digital inputs v ih high level input voltage dvdd > 2.3 v 0.7 dvdd dvdd +0.3 v v il low level intput voltage ? 0.3 0.3 dvdd v v ih high level input voltage dvdd 2.3 v 0.8 dvdd dvdd +0.3 v v il low level intput voltage ? 0.3 0.2 dvdd v power supply avdd analog supply voltage 4.5 5 5.5 v dvdd digital supply voltage 1.65 3.3 5.5 v i avdd analog supply current avdd = 5 v, f sample = 3 msps 24 ma avdd = 5 v, no conversion 8 ma avdd = 5 v, power down ( pd/ rst low) 1 a i dvdd digital supply current dvdd = 3.3 v, c sdo-x/y = 10 pf 0.75 ma psrr (3) power supply rejection ratio 100mvp-p ripple on avdd of frequency < 100khz 70 db (1) all specifications expressed in decibels (db) refer to the full-scale input (fsr) and are tested with an input signal 0.5 db below full- scale, unless otherwise specified. 6.6 electrical characteristics: ADS9224R all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 to 5.5 v, and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v parameter test conditions min typ max unit dc accuracy resolution, no missing codes 16 bit dnl differential nonlinearity ? 0.99 0.5 0.99 lsb inl integral nonlinearity ? 2 1 2 lsb e o offset error ? 6 1 6 lsb g e cummulative gain error for adc_x and refbuf_x ? 0.05 0.01 0.05 %fsr g e / t gain drift 5 ppm/ c transition noise mid-code, pfs-1000, nfs+1000 tbd lsb cmrr (1) common-mode rejection ratio f in = dc to 1-mhz, v in = 100 mvp-p 80 db ac accuracy snr (1) signal-to-noise ratio f in = 2 khz 89 93.5 db f in = 100 khz 90.5 db f in = 1400 khz 88.5 db advance information
8 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics: ADS9224R (continued) all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 to 5.5 v, and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v parameter test conditions min typ max unit (2) calculated on the first nine harmonics of the input frequency. sinad (1) (2) signal-to-noise plus distortion f in = 2 khz 90.8 db f in = 100 khz 90.3 db f in = 1400 khz 83 db thd (1) (2) total harmonic distortion f in = 2 khz ? 110 db f in = 100 khz ? 105 db f in = 1400 khz -85 db sfdr (1) spurious-free dynamic range f in = 2 khz 115 db f in = 100 khz 110 db f in = 1400 khz 90 db isoxt (1) channel-to-channel isolation f in_adca = 15 khz at 10% fsr, f in_adcb = 25 khz at 100% fsr ? 110 db (1) all specifications expressed in decibels (db) refer to the full-scale input (fsr) and are tested with an input signal 0.5 db below full- scale, unless otherwise specified. (2) calculated on the first nine harmonics of the input frequency. 6.7 electrical characteristics: ads9234r all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 to 5.5 v, and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v parameter test conditions min typ max unit dc accuracy resolution, no missing codes 14 bit dnl differential nonlinearity ? 0.99 0.15 0.99 lsb inl integral nonlinearity ? 1 0.3 1 lsb e o offset error ? 2.5 0.8 2.5 lsb g e cummulative gain error for adc_x and refbuf_x ? 0.05 0.01 0.05 %fsr g e / t gain drift 5 ppm/ c transition noise mid-code, pfs-1000, nfs+1000 tbd lsb cmrr (1) common mode rejection ratio f in = dc to 1-mhz, v in = 100 mvp-p 75 db ac accuracy snr (1) signal-to-noise ratio f in = 2 khz 82 85.6 db f in = 100 khz 84 db f in = 1400 khz 82 db sinad (1) (2) signal-to-noise plus distortion f in = 2 khz 85.6 db f in = 100 khz 84 db f in = 1400 khz 80 db thd (1) (2) total harmonic distortion f in = 2 khz ? 106 db f in = 100 khz ? 105 db f in = 1400 khz ? 85 db sfdr (1) spurious-free dynamic range f in = 2 khz 108 db f in = 100 khz 107 db f in = 1400 khz 90 db isoxt (1) channel-to-channel isolation f in_adca = 15 khz at 10% fsr, f in_adcb = 25 khz at 100% fsr ? 110 db advance information
9 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) see switching characteristics (2) see protocols for reading from the device for t read (3) other parameters are the same as the spi-compatible and parallel byte protocols. 6.8 timing requirements all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 v to 5.5 v, and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v min nom max unit conversion control and data transfer (see figure 1 and figure 2 ) t d_convst_cs delay time: convst high to cs falling for zero cycle latency (zone 1 transfer) t drdy (1) ns t d_convst_cs delay time: convst high to cs falling for zone 2 transfer 15 180 ns t wl_convst pulse duration : convst low 15 ns t wh_convst pulse duration : convst high 15 ns t cycle time between two adjacent convst rising edges for zero cycle latency (zone 1 transfer) t drdy +t read (2) ns t cycle time between two adjacent convst rising edges for zone 2 transfer 333 ns spi-compatible and parallel byte protocols (see figure 3 ) t clk serial clock time period 1/ f clk t ph_clk sclk high time 0.45 t clk 0.55 t clk ns t pl_clk sclk low time 0.45 t clk 0.55 t clk ns t su_csck setup time: cs faling to first sclk capture edge 12 ns t su_ckdi setup time: sdi data valid to sclk capture edge 1.5 ns t ht_ckdi hold time: sclk capture edge to previous data valid on sdi 1.5 ns t ht_ckcs delay time: last sclk capture edge to cs rising 7 ns f clk serial clock frequecny for spi protocols with single data rate 60 mhz f clk serial clock frequecny for spi protocols with double data rate 22 mhz f clk serial clock frequecny for parallel byte protocol 45 mhz clock re-timer protocol with strobe = sclk (external clock) (3) (see figure 4 ) f clk serial clock frequency with single data rate 60 mhz f clk serial clock frequency with double data rate 22 mhz asynchronous reset and power down timing (see figure 6 ) t wl-rst pulse duration (low) for reset 50 500 ns t wl-pd-min minimum pulse duration (low) for power down 1000 ns advance information
10 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) other parameters are the same as the spi-compatible and parallel byte protocols. (2) with c refp_x = 10 f 6.9 switching characteristics all minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.5 v to 5.5 v, dvdd = 2.35 v to 5.5 v, and f sample = 3 msps (unless otherwise noted); typical values are at t a = 25 c, avdd = 5 v, and dvdd = 3.3 v min typ max unit conversion control and data transfer (see figure 1 and figure 2 ) t drdy data ready time for present sample: convst high to ready high with zero cycle latency (zone 1 transfer) for ads9224x (16-bit) 300 ns data ready time for present sample: convst high to ready high with zero cycle latency (zone 1 transfer) for ads9234x (14-bit) 285 ns spi-compatible and parallel byte protocols (see figure 3 ) t den_csdo delay time: cs falling to data valid on sdo-x 12 ns t dz_csdo delay time: cs rising edge to sdo-x tristate 12 ns t d_ckdo delay time: sclk launch edge to next data valid on sdo-x for spi-compatible protocols with single data rate tbd 15.8 ns t d_ckdo delay time: sclk launch edge to next data valid on sdo-x for spi-compatible protocols with double data rate tbd 21 ns t d_ckdo delay time: sclk launch edge to next data valid on sdo-x for parallel byte protocol tbd 21 ns clock re-timer protocol with strobe = sclk (external clock) (1) (see figure 4 ) t off_strobe_do time offset: strobe edge to next data valid on sdo-x -2.5 2.5 ns t d_cs_ready delay time: cs rising to ready displaying internal device state 13.5 ns t d_ckstrobe_r delay time: sclk rising edge to strobe rising 21.5 ns t d_ckstrobe_f delay time: sclk falling edge to strobe falling 21.5 ns t ph_strobe strobe output high time 0.45 t str 0.55 t str ns t pl_strobe strobe output low time 0.45 t str 0.55 t str ns clock re-timer protocol with strobe = internal clock. (1) (see figure 5 ) t d_cs_strobe delay time : cs falling to 1 st strobe rising 15 50 ns t off_strobe_do time offset : strobe edge to next data valid on sdo-x -2.5 2.5 ns t d_cs_ready delay time: cs rising to ready displaying internal device state 13.5 ns t intclk intclk period 15 ns t str strobe period (intclk) 15 ns intclk/2 30 ns intclk/4 60 ns t wh_str strobe high period 0.45 t str 0.55 t str ns t wl_str strobe low period 0.45 t str 0.55 t str ns asynchronous reset and power down timing (see figure 6 ) t rst-wkup wake up time from reset 1 s t pd-wkup (2) wake up time from power down 25 ms advance information
11 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the ready output is required for data transfer with zero cycle latency. the strobe output is required only for clock re-timer (crt) protocols. figure 1. conversion control and data transfer with zero cycle latency (zone 1 transfer) (1) the ready output is not required for zone 2 data transfer. the strobe output is required only for clock re-timer protocols. figure 2. conversion control and data transfer with wider read cycle (zone 2 transfer) sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? output data 6dpsoh1? convst t drdy t wh _ convst ready/strobe (1) zone 1 t wl_convst t d_convst_cs t d_convst_cs-min adcst (internal) t acq $ftxlvlwlrqri6dpsoh1 +1 ? advance information sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? output data 6dpsoh1 -1 ? convst t wh _ convst zone 2 ready/strobe (1) t wl_convst t d _ convst _ cs adcst (internal) t acq acquisition of 6dpsoh1 +1 ? t d_convst_cs-min t d_convst_cs-max t read-max
12 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the sclk polarity, launch edge, and capture edge depend on the spi protocol selected. ddr is not supported with the parallel byte protocol. figure 3. spi-compatible and parallel byte protocols timing figure 4. clock re-timer protocol (external clock) timing sclk (1) sdo-x cs t su_csck t ht_ckcs t den_csdo t dz_csdo sclk (1) sdi sdo-x t ph_clk t pl_clk t clk t su_ckdi t ht_ckdi t d_ckdo sdo-x t d_ckdo t d_ckdo (sdr) (ddr) sclk sdo-x cs t su_csck t ht_ckcs t den_csdo t dz_csdo sclk sdo-x (ddr) ready/ strobe t d_cs_ready t ph_ck t pl_ck t clk t d_ckstrobe_r t d_ckstrobe_f sdo-x (sdr) ready/ strobe t off_strobe_do t off_strobe_do t off_strobe_do advance information
13 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 5. clock re-timer protocol (internal clock) timing figure 6. asynchronous reset and power-down timing sdo-x cs sdo-x (ddr) t str sdo-x (sdr) t d_cs_strobe ready/ strobe ready/ strobe t off_strobe_do t off_strobe_do t off_strobe_do t ph_strobe t pl_strobe t d_cs_ready t den_csdo t dz_csdo t rst-wkup t wl-rst-max t wl-rst-min rst/pd adcst(internal) t pd-wkup t wl-pd rst/pd reset power down t wl-rst adcst(internal) device in acquisition device in acquisition advance information
14 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the device belongs to a family of dual, high-speed, simultaneous-sampling, analog-to-digital converters (adcs). the device supports fully differential input signals and a full-scale input range equal to 3.2678 v ref . when a conversion is initiated, the input between the ainp_x and ainm_x pins is sampled on the internal capacitor array. the device uses an internal clock to perform conversions. during the conversion process, both analog inputs are disconnected from the internal circuit. at the end of conversion process, the device reconnects the sampling capacitors to the ainp_x and ainm_x pins and enters an acquisition phase. the device includes reference buffers to provide the charge required by the adcs during conversion. the device includes a reference voltage for the adcs. the enhanced serial programming interface (spi) digital interface is backward-compatible with traditional spi protocols. configurable features simplify board layout, timing, and firmware and support high throughput at lower clock speeds, thus allowing an easy interface with a variety of microcontrollers, digital signal processors (dsps), and field-programmable gate arrays (fpgas). the device also provides a byte mode and a wide read cycle to reduce the clock frequency required for data transfer. the device includes a clock re-timer (crt) to enable data transfer through digital isolators. the device also supports double data rate (ddr) with spi-compatible serial interface modes and with a clock re-timer. 7.2 functional block diagram refbuf_a serial interface pd/rst ainp_a avdd dvdd refp_b reference voltage 2.5 v ainm_a adc_a ainp_b ainm_b adc_b refbuf_b avdd avdd refp_a refout refout refm_b refm_a convst cs sclk sdi ready/strobe sdo-x/y sdo-x/y avdd gnd refby2 refby2 avdd advance information
15 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description from a functional perspective, the device is comprised of seven modules: two converters (adc_a, adc_b), two reference buffers (refbuf_a, refbuf_b) , the refby2 buffer, the reference voltage, and the serial interface, as shown in the functional block diagram section. the converter module samples and converts the analog input into an equivalent digital output code. the reference buffers provide the charge required by the converters for the conversion process. the serial interface module facilitates communication and data transfer between the device and the host controller. the refby2 buffer provides the common-mode voltage for the amplifiers input driving the analog of the device. the reference voltage is used by the converters for conversion process. 7.3.1 converter modules as shown in figure 7 , both converter modules sample the analog input signal (provided between the ainp_x and ainm_x pins), compare this signal with the reference voltage (between the pair of refp_x and refm_x pins), and generate an equivalent digital output code. the converter modules receive pd/ rst and the convst inputs from the interface module, and output the adcst signal and the conversion result back to the interface module. figure 7. converter modules 7.3.1.1 analog input with sample-and-hold this device supports unipolar, fully differential, analog input signals. figure 8 shows a small-signal equivalent circuit of the sample-and-hold circuit. each sampling switch is represented by a resistance (r s1 and r s2 , typically 120 ) in series with an ideal switch (sw 1 and sw 2 ). the sampling capacitors, c s1 and c s2 , are typically 16 pf. figure 8. analog input structure for converter module advance information ainp_x gnd refp_x agnd sample- and-hold circuit avdd adc_a osc serial interface dvdd pd/rst convst cs sclk sdi sdo-x/y ready/strobe conversion result adcst convst rst refm_x ainm_x adc_b sdo-x/y ainp_x ainm_x c s1 avdd device in hold mode c s2 r s1 1 pf 1 pf sw 1 r s2 sw 2 gnd gnd
16 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) during the acquisition process, both inputs are individually sampled on c s1 and c s2 , respectively. during the conversion process, both converters convert for the respective voltage difference between the sampled values: v ainp_x ? v ainm_x . equation 1 and equation 2 provide the full-scale input range (fsr) and common-mode voltage (vcm), supported at the analog inputs for reference voltage (v ref ) on the refout pin. fsr = 1.6384 v ref = 3.2768 v ref (1) v cm = 0.8192 v ref 0 .2 v (2) 7.3.1.2 adc transfer function this device supports unipolar, fully differential input signals. the device output is in two's compliment format. table 1 and figure 9 show the ideal transfer characteristics for the device. equation 3 gives the least significant bit (lsb) for the adc. 1 lsb = fsr / 2 r where ? fsr is defined in equation 1 ? r = resolution of the device (3) figure 9. ideal transfer characteristics table 1. transfer characteristics step input voltage (ainp_x-ainm_x) code description ideal output code (r = 16) ideal output code (r = 14) a ? (1.6384 v ref ? 1 lsb) nfsc negative full-scale code 8000 2000 b 0 lsb to 1 lsb mc mid code 0000 0000 c (1.6384 v ref ? 1 lsb) pfsc positive full-scale code 7fff 1fff advance information pfsc analog input (ainp_x ainm_x) mc adc code (hex) v in nfsc b a c
17 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.2 internal reference voltage the device features an internal reference source with a nominal output value of 2.5 v. the refout pin is an output with the internal reference value. a 1- f decoupling capacitor (c refout ), as shown in figure 10 , is recommended to be placed between the refout pin and gnd pin. the capacitor must be placed as close to the refout pin as possible. the output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. the initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. heating the device when being soldered to a printed circuit board (pcb) and any subsequent solder reflow is a primary cause for shifts in the v ref value. figure 10. connection diagram for reference and reference buffers 7.3.3 reference buffers on the convst rising edge, both converters start converting the sampled value on the analog input, and the internal capacitors are switched to the refp_x pins. most of the switching charge required during the conversion process is provided by the external decoupling capacitor c refp_x . if the charge lost from c refp_x is not replenished before the next convst rising edge, the subsequent conversion occurs with this different reference voltage and causes a proportional error in the output code. to eliminate these errors, the internal reference buffers of the device maintains the voltage on the refp_x pins. the reference buffers have a gain of g refbuf , as specified in the specifications section. the voltage at the refp_x pins can be calculated as v refp_x = g refbuf v ref . all performance characteristics of the device are specified with the internal reference buffer and a specified value of c refp_x . as shown in figure 10 , place a decoupling capacitor c refp_x between the refp_x pins and the refm_x pin as close to the device as possible. 7.3.4 refby2 buffer the device includes a refby2 buffer for setting the common-mode voltage required by the converter modules. the refby2 output can be provided to the v ocm pin of the fully differential amplifiers (similar to the ths4551 ). the refby2 output can be increased by 100 mv (for specifications of the refby2 output, see the specifications section) for providing headroom from gnd for the fully differential amplifier. to increase the refby2 output, set the en_refby2_offset bit to 1 in the refby2_offset register . figure 11 depicts a block diagram for the refby2 buffer. advance information refout refm_x gnd avdd + refp_x refbuf_x g refbuf c refp_x internal v ref 2.5 v c refout
18 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 11. refby2 buffer 7.3.5 data averaging the device can be configured to average two or four samples and provide the averaged value as output data. to configure the data averaging, configure the data_avg_cfg register . 7.3.5.1 averaging of two samples to enable averaging of two samples, set the en_data_avg bits in the data_avg_cfg register to 10b. in this mode, the device averages two samples and provides the average of two samples as output data. the output data rate reduces by a factor of two. in this mode, the host must provide two pulses separated by a time of t cycle (see t cycle for a zone 2 transfer in the specifications section) on the convst pin. the device sets the ready pin high after a time of t drdy (see t drdy in the specifications section) from the second rising edge on the convst pin. after the ready pin is set high, the host can read the data by using one of the protocols for reading from the device . the host can read the data while providing the two convst pulses for acquiring the next two samples. the host must keep t read < [2 t cycle ]. figure 12 provides the timing for the averaging of two samples. figure 12. timing for averaging of two samples sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? convst sample 1 +2 ? sample 1 +3 ? ready/strobe output data = [ 6dpsoh1? + 6dpsoh1 +1 ? ]/2 t drdy t wl_convst gnd refp_a + refby2 refby2 c refby2 refm_a r r en_refby2_ offset avdd refby2 with en_refby2_offset = 0 gnd refby2 with en_refby2_offset = 1 v refp_a /2 100 mv copyright ? 2017, texas instruments incorporated advance information
19 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.5.2 averaging of four samples to enable averaging of four samples, set the en_data_avg bits in the data_avg_cfg register to 11b. in this mode, the device averages four samples and provides the average of four samples as output data. the output data rate reduces by a factor of four. in this mode, the host must provide four pulses separated by a time of t cycle (see t cycle for a zone 2 transfer in the specifications section) on the convst pin. the device sets the ready pin high after a time of t drdy (see t drdy in the specifications section) from the fourth rising edge on the convst pin. after the ready pin is set high, the host can read the data by using one of the protocols for reading from the device . the host can read the data while providing the four convst pulses for acquiring the next four samples. the host must keep t read < [4 t cycle ]. figure 13 provides the timing for the averaging of four samples. figure 13. timing for averaging of four samples 7.4 device functional modes as shown in figure 14 , this device supports three functional states: rst or power-down, acq, and cnv. the device state is determined by the status of the convst and pd/ rst control signals provided by the host controller. figure 14. device functional states advance information acq cnv rst or power down pd/rst falling edge pd / rst rising edge start of conversion power up or start of acquisition pd / rst falling edge sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? convst sample 1 +2 ? sample 1 +3 ? sample 1 +4 ? sample 1 +5 ? sample 1 +6 ? sample 1 +7 ? ready/strobe output data = [ 6dpsoh1? + 6dpsoh1 +1 ? + 6dpsoh1 +2 ? + 6dpsoh1 +3 ? ]/4 t drdy t wl_convst
20 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.1 acq state in acq state, the device acquires the analog input signal. the device enters acq state at power-up, when coming out of power down, after any asynchronous reset, and by the adcst signal (internal). a pd/ rst falling edge takes the device from acq state to rst state. a convst rising edge takes the device from acq state to cnv state. 7.4.2 cnv state the device moves from acq state to cnv state and starts conversion on a rising edge of a convst pin. the conversion process uses an internal clock. the host must provide a minimum time of t cycle between two subsequent start of conversions. 7.4.3 reset or power-down the pd/ rst pin is an asynchronous digital input for the device. the pulse duration (low) on the pd/ rst pin decides the state for the device (reset or power-down). figure 15 provides the timing diagram for these states. on power-up or after reset the device supports the spi-00-s protocol for configuring the device and the spi-00- s-sdr protocol for reading the data from the device. see the protocols for reading from the device and protocols for configuring the device sections for details. figure 15. reset or power down 7.4.3.1 reset to enter reset state, the host controller pulls and keeps the pd/ rst pin low for a duration of t wl_rst (t wl_rst-min t wl_rst t wl_rst-max ). in reset state, the device terminates the ongoing conversion or acquisition process and all configuration registers (see the register maps section) are reset to their default values. to exit reset state, the host controller pulls the pd/ rst pin high. after a delay of t rst-wkup , the device enters acq state. 7.4.3.2 power-down to enter power-down state, the host controller pulls and keeps the pd/ rst pin low for a minimum duration of t wl_pd . in power-down state, all device blocks are powered down and all configuration registers (see the register maps section) are reset to their default values. to exit power-down state, the host controller pulls the pd/ rst pin high. after a delay of t pd-wkup , the device powers up and enters acq state. t rst-wkup t wl-rst-max t wl-rst-min rst/pd adcst(internal) t pd-wkup t wl-pd rst/pd reset power down t wl-rst adcst(internal) device in acquisition device in acquisition advance information
21 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.4 conversion control and data transfer frame the device supports two modes of conversion control and data transfer, one with zero cycle latency (zone 1 transfer) and another with a wide read cycle (zone 2 transfer). 7.4.4.1 conversion control and data transfer frame with zero cycle latency (zone 1 transfer) in this mode of conversion control and data transfer, the device starts conversion on the rising edge of convst. the convst pin can be pulled low after a minimum time of t wh_convst . after the conversion is finished, the rising edge of the ready/strobe pin indicates that the data are ready and the data can be read by the host. after the ready pin is set high, as shown in figure 16 , the host must pull cs low and provide clocks on the sclk pin to read the data in zone 1 without cycle latency. for a zone 1 transfer, the host must provide a minimum delay time of t d_convst_cs (= t drdy ) between the rising edge of convst and the falling edge of cs. the data for the present sample (sample n) is provided by the device on the sdo pins. after all bits are read, the host can pull the cs pin high to end the data transfer frame. after pulling cs high, the host can pull the convst pin high to start the next conversion. the host must keep the sdi pin low (nop0) or high (nop1) for conversion control and for getting conversion results from the device. in this mode of conversion control, the time between two adjacent rising edges of the convst signal (t cycle ) is determined as t cycle = t drdy + t read . (1) the ready output is required for data transfer with zero cycle latency. the strobe output is required only for clock re-timer (crt) protocols. see the ready/strobe output section for details. (2) for t read with different data transfer protocols; see the protocols for reading from the device section. (3) f sample = 1 / t cycle . figure 16. conversion control and data transfer frame with zero cycle latency (zone 1 transfer) sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? output data 6dpsoh1? convst t drdy t wh _ convst ready/strobe (1) zone 1 t wl_convst t d_convst_cs t d_convst_cs-min adcst (internal) t acq $ftxlvlwlrqri6dpsoh1 +1 ? advance information
22 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.4.2 conversion control and data transfer frame with wide read cycle (zone 2 transfer) in this mode of conversion control and data transfer, the device starts conversion on the rising edge of convst. the convst pin can be pulled low after a minimum time of t wh_convst . after a time of t d_convst_cs (see t d_convst_cs for zone 2 transfer in the specifications section), the host must pull cs low and provide clocks on the sclk pin to read the data in zone 2. as shown in figure 17 , a zone 2 transfer provides more read time (t read ). the read time available for reading data is maximized when t d_convst_cs is set to the minimum permissible value. the data for the previous sample (sample n-1) is provided by the device on the sdo pins. after all bits are read, the host can pull the cs pin high to end the data transfer frame. after pulling cs high, the host can pull the convst pin high to start the next conversion. in this mode of conversion control, a minimum time of t cycle (see t cycle for zone 2 transfer in the specifications section) is required between two adjacent rising edges of the convst signal. the host must keep the sdi pin low (nop0) or high (nop1) for conversion control and for getting conversion results from the device. (1) the ready output is not required for zone 2 data transfer. the strobe output is required only for clock re-timer (crt) protocols. see the ready/strobe output section for details. (2) for t read with different data transfer protocols; see the protocols for reading from the device section. (3) f sample = 1 / t cycle . figure 17. conversion control and data transfer frame with wide read cycle (zone 2 transfer) note for optimum performance with zone 2 transfer, ti recommends masking the ready output by setting the ready_mask bit in the output_data_word_cfg register and using a data transfer protocol with a bus width of more than 2 sdos or the parallel byte protocol to keep [t d_convst_cs + t read ] below 150 ns. see the protocols for reading from the device section for details on different protocols for reading the data. advance information sclk sdo-xx cs t cycle t read sample 1? sample 1 +1 ? output data 6dpsoh1 -1 ? convst t wh _ convst zone 2 ready/strobe (1) t wl_convst t d _ convst _ cs adcst (internal) t acq acquisition of 6dpsoh1 +1 ? t d_convst_cs-min t d_convst_cs-max t read-max
23 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the device provides register data in the output data word during register read operation. (2) when a fixed pattern data is enabled, the device provides a fixed pattern in the output data word. 7.5 ready/strobe output the ready/strobe pin has multiple functions. the ready and strobe signals are multiplexed to this pin. when cs is low, strobe is output and when cs is high, ready is output. 7.5.1 ready output after power-up or after exiting power-down (a rising edge on pd/ rst), the ready signal is set high. after a time of 0.9 ms, this signal goes low, indicating that the device is initialized and the registers can be configured. however, conversions can only be performed with the desired accuracy only after a time of t pd-wkup (see the specifications section). after power-up, ready indicates that data are available for readout. ready is set low at the next falling edge of cs. for zone 2 transfer, ti recommends masking the ready output by setting the ready_mask bit in the output_data_word_cfg register . 7.5.2 strobe output in clock re-timer protocols, the device sends out data on the sdo lines with synchronized clock on the strobe line. the data are synchronized to the rising edges of the strobe pulses. in crt protocols, the host can use the strobe output for latching the data. the strobe for the crt protocols is either derived from the external sclk provided by the host or from the internal oscillator. the strobe signal is held low for protocols other than the crt protocols. 7.6 programming 7.6.1 output data word the output data word, as shown in table 2 , consists of a conversion result of n bits, where n is the width of the output data word. the output data word is provided on data lines (sdo-xx) for each adc. table 2. output data word device resolution of device (r) width of output data word (n) content of output data word (1) (2) msb of conversion result with left alignment msb of conversion result with right alignment ads9224 r 16 16 16-bit conversion in 2's compliment format d n-1 (= d 15 ) d n-1 (= d 15 ) ads9234 r 14 16 14-bit conversion in 2's compliment format d n-1 (= d 15 ) d n-3 (= d 13 ) for ads9234 r devices with 14-bit resolution, the output data word can be left-aligned or right-aligned by configuring the data_right_aligned bit. with left alignment, the device appends zeros in the end of the output data word. with right alignment, the device appends msbs in the beginning of the output data word. figure 18 shows the data alignment in the data output word. figure 18. data alignment for ads9234 r devices advance information d 13 d 12 d 11 0 0 d 13 d 13 d 12 d 2 d 1 d 0 d 13 d 0 d 1 left aligned data with zeros appended at the end right aligned data with msbs appended in the beginning ( sign extension)
24 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for legacy spi-compatible protocols, set the sdo_protocol bits in protocol_cfg register to 000b. (2) configure the spi_cpol and spi_cpha bits in the protocol_cfg register for the desired cpol and cpha. (3) with sclk 30 mhz, ti recommends data capture on the launch edge for the next bit. (4) with sclk < 30 mhz, data can be captured either on the same edge as the sclk phase or on the launch edge for the next bit. (5) t read is the read time for reading the 16-bit output data word. k = (t su_csck + t ht_ckcs ). (6) for ads9234 r devices, the read time for reading the 14-bit output data word is [13.5 t clk + k]. 7.6.2 data transfer protocols this device features an enhanced-spi digital interface that allows the host controller to operate at slower sclk speeds and still achieve the required throughput and response time. the enhanced-spi digital interface module offers three options to reduce the sclk speed required for data transfer: ? increase the width of the output data bus (dual sdo, quad sdo, or parallel byte) ? enable double data rate (ddr) transfer ? wider read cycle by extending the data transfer window (zone 2 transfer) these three options can be combined to achieve further reduction in sclk speed. 7.6.2.1 protocols for reading from the device the protocols for the data-read operation can be broadly classified into five categories: 1. legacy, spi-compatible protocols (spi-xy-s-sdr) 2. spi-compatible protocols with bus width options and single data rate (spi-xy-d-sdr and spi-xy-q-sdr) 3. spi-compatible protocols with bus width options and double data rate (spi-x1-s-ddr, spi-x1-d-ddr, and spi-x1-q-ddr) 4. clock re-timer (crt) protocols (crt-s-sdr, crt-d-sdr, crt-q-sdr, crt-s-ddr, crt-d-ddr, and crt-q-ddr) 5. parallel byte protocol (pb-xy-ab-sdr, pb-xy-aa-sdr) 7.6.2.1.1 legacy, spi-compatible protocols (spi-xy-s-sdr) the device supports legacy, spi-compatible protocols with all combinations of clock phase and polarity. in this data transfer protocol, the device provides data from adc_a on sdo-0a and data from adc_b on sdo-0b. on power-up or after reset, the device supports the spi-00-s-sdr protocol for reading data from the device. table 3 provides the details of different legacy spi protocols to read data from the device. table 3. spi-xy-s-sdr protocols for reading from device protocol (1) sclk polarity (cpol (2) ) sclk phase (cpha (2) ) (3) (4) msb launch edge bus width t read (5) (6) timing diagram spi-00-s-sdr low (cpol= 0) rising (cpha = 0) cs falling 1 [15.5 t clk + k] figure 19 spi-01-s-sdr low (cpol= 0) falling (cpha = 1) 1 st sclk rising 1 [15.5 t clk + k] figure 20 spi-10-s-sdr high (cpol= 1) falling (cpha = 0) cs falling 1 [15.5 t clk + k] figure 19 spi-11-s-sdr high (cpol= 1) rising (cpha = 1) 1 st sclk falling 1 [15.5 t clk + k] figure 20 advance information
25 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for spi-compatible protocols with bus width options and sdr, set the sdo_protocol bits in the protocol_cfg register to 000b. (2) configure the spi_cpol and spi_cpha bits in the protocol_cfg register for the desired cpol and cpha. (3) with sclk 30 mhz, ti recommends data capture on the launch edge for the next bit. (4) with sclk < 30 mhz, data can be captured either on the same edge as the sclk phase or on the launch edge for the next bit. (5) for configuring the bus width, configure the bus_width register . (6) t read is the read time for reading the 16-bit output data word. k = (t su_csck + t ht_ckcs ). (7) for ads9234 r devices, the read time for reading the 14-bit output data word is [6.5 t clk + k] for a bus width of 2 and [3.5 t clk + k] for a bus width of 4. figure 19 and figure 20 show timing diagrams for the spi-00-s-sdr, spi-10-sdr and spi-01-s-sdr, spi-11- sdr protocols, respectively. figure 19. spi-00-s-sdr and spi-10-sdr protocols figure 20. spi-01-s-sdr and spi-11-sdr protocols 7.6.2.1.2 spi-compatible protocols with bus width options and single data rate (spi-xy-d-sdr and spi-xy-q-sdr) in this data transfer protocol, the bus width of reading data from each adc can be increased to two sdos or four sdos. all combinations of clock phase and polarity are supported. the read time required for reading the output data word reduces with increases in bus width and, thus, t cycle for zone 1 transfer reduces. the sdos that are not enabled by the bus_width register are set to tri-state. table 4 provides the details of different spi protocols with bus width options and single data rate to read data from the device. table 4. spi-xy-d-sdr and spi-xy-q-sdr protocols for reading from device protocol (1) sclk polarity (cpol) (2) sclk phase (cpha) (3) (4) msb launch edge bus width (5) t read (6) (7) timing diagram spi-00-d-sdr low (cpol = 0) rising (cpha = 0) cs falling 2 [7.5 t clk + k] figure 21 spi-01-d-sdr low (cpol = 0) falling (cpha = 1) 1 st sclk rising 2 [7.5 t clk + k] figure 22 spi-10-d-sdr high (cpol = 1) falling (cpha = 0) cs falling 2 [7.5 t clk + k] figure 21 spi-11-d-sdr high (cpol = 1) rising (cpha = 1) 1 st sclk falling 2 [7.5 t clk + k] figure 22 spi-00-q-sdr low (cpol = 0) rising (cpha = 0) cs falling 4 [3.5 t clk + k] figure 23 spi-01-d-sdr low (cpol = 0) falling (cpha = 1) 1 st sclk rising 4 [3.5 t clk + k] figure 24 spi-10-d-sdr high (cpol = 1) falling (cpha = 0) cs falling 4 [3.5 t clk + k] figure 23 spi-11-d-sdr high (cpol = 1) rising (cpha = 1) 1 st sclk falling 4 [3.5 t clk + k] figure 24 cs cpol = 0 cpol = 1 sclk sdo-0a d n-1 a sdo-0b d n-2 a d 0 a d n-3 a d n-1 b d n-2 b d 0 b d n-3 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit advance information cs sclk cpol = 0 cpol = 1 sdo-0a d n-1 a sdo-0b d n-2 a d 0 a d n-3 a d n-1 b d n-2 b d 0 b d n-3 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit
26 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 21 , figure 22 , figure 23 , and figure 24 show timing diagrams for the spi-00-d-sdr and spi-10-d-sdr, spi-01-d-sdr and spi-11-d-sdr, spi-00-q-sdr and spi-10-q-sdr, and spi-01-q-sdr and spi-11-q-sdr protocols, respectively. figure 21. spi-00-d-sdr and spi-10-d-sdr protocols figure 22. spi-01-d-sdr and spi-11-d-sdr protocols figure 23. spi-00-q-sdr and spi-10-q-sdr protocols figure 24. spi-01-q-sdr and spi-11-q-sdr protocols sclk sdo-3a d n-1 a sdo-0b cs d n-5 a d 3 a d n-9 a d n-4 b d n-8 b d 0 b d n-12 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 sdo-2a d n-2 a d n-6 a d 2 a d n-10 a sdo-1b d n-3 b d n-7 b d 1 b d n-11 b sdo-1a d n-3 a d n-7 a d 1a d n-11 a sdo-0a d n-4 a d n-8 a d 0 a d n-12 a sdo-2b d n-2 b d n-5 b d 2 b d n-10 b sdo-3b d n-1 b d n-5 b d 3 b d n-9 b sclk sdo-3a d n-1 a sdo-0b cs d n-5 a d 3 a d n-9 a d n-4 b d n-8 b d 0 b d n-12 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 sdo-1b d n-3 b d n-7 b d 1 b d n-11 b sdo-2a d n-2 a d n-6 a d 2 a d n-10 a sdo-1a d n-3 a d n-7 a d 1 a d n-11 a sdo-0a d n-4 a d n-8 a d 0 a d n-12 a sdo-2b d n-2 b d n-6 b d 2 b d n-10 b sdo-3b d n-1 b d n-5 b d 3 b d n-9 b sclk sdo-1a d n-1 a sdo-0b cs d n-3 a d 1a d n-5 a d n-2 b d n-4 b d 0 b d n-6 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 sdo-0a d n-2 a d n-4 a d 0 a d n-6 a sdo-1b d n-1 b d n-3 b d 1 b d n-5 b sdo-1a d n-1 a sdo-0b cs d n-3 a d 1 a d n-5 a d n-2 b d n-4 b d 0 b d n-6 b ready/strobe end of frame sclk launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 sdo-1b d n-1 b d n-3 b d 1 b d n-5 b sdo-0a d n-2 a d n-4 a d 0 a d n-6 a advance information
27 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for spi-compatible protocols with bus width options and ddr, set the sdo_protocol bits in the protocol_cfg register to 001b. (2) configure the spi_cpol bits in the protocol_cfg register for the desired cpol. the device supports cpha = 1 only for spi- compatible protocols with bus width options and ddr. (3) for configuring the bus width, configure the bus_width register . (4) t read is the read time for reading the 16-bit output data word. k = (t su_csck + t ht_ckcs ). (5) for ads9234 r devices, the read time for reading the 14-bit output data word is [7.5 t clk + k] for a bus width of 1, [3.5 t clk + k] for a bus width of 2, and [3 t clk + k] for a bus width of 4. 7.6.2.1.3 spi-compatible protocols with bus width options and double data rate (spi-x1-s-ddr, spi-x1-d-ddr, spi-x1-q-ddr) in this data transfer protocol, the data rate for data transfer can be increased to double data rate. with double data rate, the device launches data on both edges (rising and falling) of the sclk. the device supports both polarities of the clock and only one phase of clock (cpha = 1). the read time required for reading the output data word reduces with increases in bus width and data rate. the sdos that are not enabled by the bus_width register are set to tri-state. table 5 provides the details of different spi protocols with bus width options and double data rate to read data from the device. table 5. spi-x1-s-ddr, spi-x1-d-ddr, and spi-x1-q-ddr protocols for reading from device protocol (1) sclk polarity (cpol) (2) sclk phase (2) msb launch edge bus width (3) t read (4) (5) timing diagram spi-01-s-ddr low (cpol = 0) falling (cpha = 1) 1 st sclk rising 1 [9 t clk + k] figure 25 spi-11-s-ddr high (cpol = 1) rising (cpha = 1) 1 st sclk falling 1 [9 t clk + k] figure 25 spi-01-d-ddr low (cpol = 0) falling (cpha = 1) 1 st sclk rising 2 [5 t clk + k] figure 26 spi-11-d-ddr high (cpol = 1) rising (cpha = 1) 1 st sclk falling 2 [5 t clk + k] figure 26 spi-01-q-ddr low (cpol = 0) falling (cpha = 1) 1 st sclk rising 4 [3 t clk + k] figure 27 spi-11-q-ddr high (cpol = 1) rising (cpha = 1) 1 st sclk falling 4 [3 t clk + k] figure 27 figure 25 , figure 26 , and figure 27 illustrate timing diagrams for the spi-01-s-ddr and spi-11-s-ddr, spi-01- d-ddr and spi-11-d-ddr, and spi-01-q-ddr and spi-11-q-ddr protocols, respectively. figure 25. spi-01-s-ddr and spi-11-s-ddr protocols figure 26. spi-01-d-ddr and spi-11-d-ddr protocols advance information sclk sdo-0a d n-1 a sdo-0b cs d n-2 a d 1 a d n-3 a d n-1 b d n-2 b d 1 b d n-3 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 d 0 a d 0 b sdo-1a d n-1 a sdo-0b cs d n-3 a d 3 a d n-5 a d n-2 b d n-4 b d 2 b d n-6 b ready/strobe end of frame sclk launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 d 1 a d 0 b sdo-0a d n-2 a d n-4 a d 2 a d n-6 a d 0 a sdo-1b d n-1 b d n-3 b d 3 b d n-5 b d 1 b
28 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 27. spi-01-q-ddr and spi-11-q-ddr protocols advance information sdo-3a d n-1 a cs d n-5 a d n-9 a sclk cpol = 0 cpol = 1 d 3 a sdo-2a d n-2 a d n-6 a d n-10 a d 2 a sdo-1a d n-3 a d n-7 a d n-12 a d 1 a sdo-0a d n-4 a d n-8 a d n-13 a d 0 a sdo-3b d n-1 b d n-5 b d n-9 b d 3 b sdo-2b d n-2 b d n-6 b d n-10 b d 2 b sdo-1b d n-3 b d n-7 b d n-12 b d 1 b sdo-0b d n-4 b d n-8 b d n-13 b d 0 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit
29 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for crt protocols with sdr, set the sdo_protocol bits in the protocol_cfg register to 010b. for crt protocols with ddr, set the sdo_protocol bits to 011b in the protocol_cfg register . (2) the device only supports cpol = 0 for crt protocols with an external clock. (3) for configuring the bus width, configure the bus_width register . (4) t read is the read time for reading the 16-bit output data word. for an external clock m = (t su_csck + t ht_ckcs ), and for an internal clock m = t d_cs_strobe . 7.6.2.1.4 clock re-timer (crt) protocols (crt-s-sdr, crt-d-sdr, crt-q-sdr, crt-s-ddr, crt-d-ddr, crt-q- ddr) in clock re-timer (crt) protocols, the device sends out data on the sdo lines with a synchronized clock on the strobe line. the data are synchronized to the rising edges of the strobe pulses. for crt protocols with a single data rate, the host can capture data on the falling edges of the strobe pulses. for double data rate, the host must capture data on both edges of strobe. the clock source for the strobe output can be selected as an external clock (sclk) or an internal clock by configuring the crt_clk_select bits in the crt_cfg register . for reading data from the device, sclk is only required when the strobe output is selected as an external clock. the sdos that are not enabled by the bus_width register are set to tri-state. table 6 provides the details of different crt protocols to read data from the device. table 6. crt-s-sdr, crt-d-sdr, crt-q-sdr, crt-s-ddr, crt-d-ddr, and crt-q-ddr protocols for reading from device protocol (1) sclk polarity (2) capture edge msb launch edge bus width (3) t read (4) timing diagram crt-s-sdr low (cpol = 0) strobe falling 1 st strobe rising 1 [15.5 t strobe + m] figure 28 crt-d-sdr low (cpol = 0) strobe falling 1 st strobe rising 2 [7.5 t strobe + m] figure 30 crt-q-sdr low (cpol = 0) strobe falling 1 st strobe rising 4 [3.5 t strobe + m] figure 32 crt-s-ddr low (cpol = 0) strobe rising and falling 1 st strobe rising 1 [7.5 t strobe + m] figure 29 crt-d-ddr low (cpol = 0) strobe rising and falling 1 st strobe rising 2 [3.5 t strobe + m] figure 31 crt-q-ddr low (cpol = 0) strobe rising and falling 1 st strobe rising 4 [1.5 t strobe + m] figure 33 figure 28 through figure 33 illustrate timing diagrams for the crt-s-sdr, crt-s-ddr, crt-d-sdr, crt-d- ddr, crt-q-sdr, and crt-q-ddr protocols, respectively. figure 28. crt-s-sdr protocol figure 29. crt-s-ddr protocol advance information sclk sdo-0a d n-1 a sdo-0b cs d n-2 a d 1 a d n-3 a d n-1 b d n-2 b d 1 b d n-3 b end of frame launch of 1 st bit launch of 2 nd bit d 0 a d 0 b ready/strobe cpol = 0 sclk sdo-0a d n-1 a sdo-0b cs d n-2 a d 0 a d n-3 a d n-1 b d n-2 b d 0 b d n-3 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit cpol = 0
30 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 30. crt-d-sdr protocol figure 31. crt-d-ddr protocol figure 32. crt-q-sdr protocol figure 33. crt-q-ddr protocol for reading data, sclk is only required when the strobe output is selected as sclk (external clock) in the crt_cfg register . however, for configuring registers, sclk is always required. d n-1 a cs d n-5 a d 3 a d n-9 a d n-4 b d n-8 b d 0 b d n-12 b ready/strobe end of frame sclk launch of 1 st bit launch of 2 nd bit d n-3 b d n-7 b d 1 b d n-11 b d n-2 a d n-6 a d 2 a d n-10 a d n-3 a d n-7 a d 1 a d n-11 a d n-4 a d n-8 a d 0 a d n-12 a d n-2 b d n-6 b d 2 b d n-10 b d n-1 b d n-5 b d 3 b d n-9 b cpol = 0 sdo-1b sdo-0b sdo-2a sdo-1a sdo-0a sdo-3b sdo-2b sdo-3a sclk sdo-1a d n-1 a sdo-0b cs d n-3 a d 1 a d n-5 a d n-2 b d n-4 b d 0 b d n-6 b ready/strobe end of frame launch of 1 st bit launch of 2 nd bit sdo-0a d n-2 a d n-4 a d 0 a d n-6 a sdo-1b d n-1 b d n-3 b d 1 b d n-5 b cpol = 0 sdo-3a d n-1 a sdo-1b cs d n-5 a d n-9 a end of frame launch of 1 st bit launch of 2 nd bit ready/strobe sdo-0b d n-2 a d n-6 a d n-10 a sdo-2a sclk d 3 a d 2 a sdo-1a d n-3 a d n-7 a d n-11 a d n-4 a d n-8 a d n-12 a sdo-0a d 1 a d 0 a sdo-3b sdo-2b d n-4 b d n-8 b d 0 b d n-12 b d n-3 b d n-7 b d 1 b d n-11 b d n-2 b d n-6 b d 2 b d n-10 b d n-1 b d n-5 b d 3 b d n-9 b cpol = 0 sdo-1a d n-1 a sdo-1b cs d n-3 a d 3 a d n-5 a d n-1 b d n-3 b d 3 b d n-5 b launch of 1 st bit launch of 2 nd bit d 1 a d 1 b ready/strobe sdo-0b d n-2 b d n-4 b d 2 b d n-6 b d 0 b d n-2 a d n-4 a d 2 a d n-6 a d 0 a sdo-0a sclk d n-1 a cs d n-3 a d 3 a d n-5 a d n-1 b d n-3 b d 3 b d n-5 b end of frame d 1 a d 1 b d n-2 b d n-4 b d 2 b d n-6 b d 0 b d n-2 a d n-4 a d 2 a d n-6 a d 0 a cpol = 0 advance information
31 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for parallel byte protocols, set the sdo_protocol bits in the protocol_cfg register to 1xxb. (2) configure the spi_cpol and spi_cpha bits in the protocol_cfg register for the desired cpol and cpha. (3) for selecting the data format for parallel byte protocols, configure the parallel_mode_data_format bits in the output_data_word_cfg register . (4) t read is the read time for reading the 16-bit output data word. k = (t su_csck + t ht_ckcs ). 7.6.2.1.5 parallel byte protocols (pb-xy-ab-sdr, pb-xy-aa-sdr in these protocols, the device sends out data from each adc on all sdo lines in a byte format. the device supports all combinations of cpol and cpha in these protocols. the format of the data byte for these protocols can be set by the parallel_mode_data_format bits in the output_data_word_cfg register . the device only supports a single data rate (sdr) in parallel byte protocols. table 7 provides the details of different parallel byte protocols to read data from the device. table 7. pb-xy-ab-sdr, pb-xy-aa-sdr protocols for reading data protocol (1) sclk polarity (cpol) (2) sclk phase (cpha) msb launch edge data format (3) t read (4) timing diagram pb-00-ab-sdr low (cpol = 0) rising (cpha = 0) cs falling ab [3.5 t clk + k] figure 34 pb-01-ab-sdr low (cpol = 0) falling (cpha = 1) 1 st sclk rising ab [3.5 t clk + k] figure 35 pb-10-ab-sdr high (cpol = 1) falling (cpha = 1) cs falling ab [3.5 t clk + k] figure 34 pb-11-ab-sdr high (cpol = 1) rising (cpha = 0) 1 st sclk falling ab [3.5 t clk + k] figure 35 pb-00-aa-sdr low (cpol = 0) rising (cpha = 0) cs falling aa [3.5 t clk + k] figure 36 pb-01-aa-sdr low (cpol = 0) falling (cpha = 1) 1 st sclk rising aa [3.5 t clk + k] figure 37 pb-10-aa-sdr high (cpol = 1) falling (cpha = 1) cs falling aa [3.5 t clk + k] figure 36 pb-11-aa-sdr high (cpol = 1) rising (cpha = 0) 1 st sclk falling aa [3.5 t clk + k] figure 37 figure 34 , figure 35 , figure 36 , and figure 37 illustrate timing diagrams for the pb-00-ab-sdr and pb-10-ab- sdr, protocols, pb-01-ab-sdr and pb-11-ab-sdr, pb-00-aa-sdr and pb-10-aa-sdr, and pb-01-aa-sdr and pb-11-aa-sdr, respectively. figure 34. pb-00-ab-sdr and pb-10-ab-sdr protocols figure 35. pb-01-ab-sdr and pb-11-ab-sdr protocols sclk sdo-7 d n-1 a sdo-0 cs d n-9 a end of frame launch of 1 st bit launch of 2 nd bit cpol = 0 cpol = 1 sdo-6 d n-2 a d n-10 a sdo-1 sdo-5 d n-3 a d n-11 a sdo-4 d n-4 a d n-12 a sdo-2 sdo-3 d 0 b d n-12 b d 1 b d n-11 b d 2 b d n-10 b d 3 b d n-9 b d n-5 a d n-6 a d n-7 a d n-8 a d 3 a d 2 a d 1a d 0 a d n-4 b d n-3 b d n-2 b d n-1 b d n-8 b d n-7 b d n-5 b d n-5 b ready/strobe advance information ready/strobe sclk cs sdo-7 d n-1 a sdo-0 d n-9 a end of frame launch of 1 st bit launch of 2 nd bit sdo-6 d n-2 a d n-10 a sdo-1 sdo-5 d n-3 a d n-11 a sdo-4 d n-4 a d n-12 a sdo-2 sdo-3 d 0 b d n-12 b d 1 b d n-11 b d 2 b d n-10 b d 3 b d n-9 b d n-5 a d n-6 a d n-7 a d n-8 a d 3 a d 2 a d 1a d 0 a d n-4 b d n-3 b d n-2 b d n-1 b d n-8 b d n-7 b d n-5 b d n-5 b cpol = 0 cpol = 1
32 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) configure the spi_cpol and spi_cpha bits in the protocol_cfg register for the desired cpol and cpha. (2) t write is the write time for writing the 16-bit data word. k = (t su_csck + t ht_ckcs ). figure 36. pb-00-aa-sdr and pb-10-aa-sdr protocols figure 37. pb-01-aa-sdr and pb-11-aa-sdr protocols 7.6.2.2 protocols for configuring the device the device supports an spi protocol for writing into the device with all combinations of clock polarity and phase. on power-up or after reset, the device supports the spi-00-s protocol for configuring the device. of as shown in table 8 , the host controller can use any of the four legacy, spi-compatible protocols (spi-00-s, spi- 01-s, spi- 10-s, or spi-11-s) to write data to the device. table 8. spi protocols for configuring the device protocol sclk polarity (cpol) (1) sclk phase (cpha) (1) msb capture edge t write (2) timing diagram spi-00-s low (cpol= 0) rising (cpha = 0) 1 st sclk rising [15.5 t clk + k] figure 38 spi-01-s low (cpol= 0) falling (cpha = 1) 1 st sclk falling [15.5 t clk + k] figure 39 spi-10-s high (cpol= 1) falling (cpha = 1) 1 st sclk falling [15.5 t clk + k] figure 38 spi-11-s high (cpol= 1) rising (cpha = 0) 1 st sclk rising [15.5 t clk + k] figure 39 ready/strobe sclk cs sdo-7 d n-1 a sdo-0 d n-9 a end of frame launch of 1 st bit launch of 2 nd bit sdo-6 d n-2 a d n-10 a sdo-1 sdo-5 d n-3 a d n-11 a sdo-4 d n-4 a d n-12 a sdo-2 sdo-3 d 0 b d n-12 b d 1 b d n-11 b d 2 b d n-10 b d 3 b d n-9 b d n-5 a d n-6 a d n-7 a d n-8 a d 3 a d 2 a d 1a d 0 a d n-4 b d n-3 b d n-2 b d n-1 b d n-8 b d n-7 b d n-5 b d n-5 b cpol = 0 cpol = 1 advance information sdo-7 d n-1 a sdo-0 d n-9 a end of frame launch of 1 st bit launch of 2 nd bit sdo-6 d n-2 a d n-10 a sdo-1 sdo-5 d n-3 a d n-11 a sdo-4 d n-4 a d n-12 a sdo-2 sdo-3 d 0 b d n-12 b d 1 b d n-11 b d 2 b d n-10 b d 3 b d n-9 b d n-5 a d n-6 a d n-7 a d n-8 a d 3 a d 2 a d 1a d 0 a d n-4 b d n-3 b d n-2 b d n-1 b d n-8 b d n-7 b d n-5 b d n-5 b ready/strobe sclk cs cpol = 0 cpol = 1
33 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated figure 38 and figure 39 show timing diagrams for the spi-00-s, spi-10-s and spi-01-s, spi-11-s protocols, respectively, for configuring the device. figure 38. spi-00-s and spi-10-s protocols for configuring the device figure 39. spi-01-s and spi-11-s protocols for configuring the device advance information sdi cs sclk c 15 c 14 c 0 c 13 capture of 1 st bit capture of 2 nd bit end of frame cpol = 0 cpol = 1 sdi c 15 cs c 14 c 0 c 13 sclk cpol = 0 cpol = 1 capture of 1 st bit capture of 2 nd bit end of frame
34 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated (1) register data for read command is provided by device in the next frame. 7.6.3 reading and writing registers to read a register or write into a register, the host must provide a 16-bit command frame c[15:0] on sdi. a command frame consists of an opcode[3:0], address[3:0], and data[7:0]. the host must keep the convst signal high for reading and writing the registers. figure 40 shows the command frame. table 9 provides the details of commands for reading and writing registers. figure 40. command frame c[15:0] table 9. commands for reading and writing registers opcode[3:0] description address[3:0] data[7:0] 0000 nop0 command for conversion control and reading conversion results n/a n/a 0001 write command for writing registers 4-bit register address 8-bit register data 0010 read (1) command for reading registers 4-bit register address 00h or ffh 0101 set bit command for setting specific bits in a register without changing the other bits 4-bit register address bits with values of 1 in data are set and bits with values of 0 in register data are not changed. 0110 clear bit command for clearing specific bits in a register without changing the other bits 4-bit register address bits with values of 1 in data are cleared and bits with values of 0 in register data are not changed. 1111 nop1 command for conversion control and reading conversion results n/a n/a 7.7 register maps table 10 lists the access codes for the ads9224 r, ads9234 r registers. table 10. ads9224 r, ads9234 r access type codes access type code description read type r r read r-w r/w read or write write type w w write reset or default value - n value after reset or the default value c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 op 3 op 2 op 1 op 0 a 3 a 2 a 1 a 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 opcode address data advance information
35 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7.1 device_status register (address = 0h) [reset = 00h] this register provides the error status of averaging mode and the status of zone 2 data transfer mode. figure 41. device_status 7 6 5 4 3 2 1 0 0 0 0 0 0 zone2_ transfer avg_error 0 r-0b r-0b r-0b r-0b r-0b r/w-0b r/w-0b r-0b table 11. device_status field descriptions bit field type reset description 7-3 reserved r 00000b reserved bits. do not write. reads return 00000b. 2 zone2_transfer r/w 0b this bit is set when the device operates in zone 2 transfer mode with a wide read cycle. this bit is a sticky bit. write 1 to this bit to clear. 1 avg_error r/w 0b this bit is set when the device receives a falling edge of cs before the current averaging operation is complete. this bit is a sticky bit. write 1 to this bit to clear. 0 reserved r 00000b reserved bits. do not write. reads return 00000b. 7.7.2 power_down_cfg register (address = 1h) [reset = 00h] this register powers down different blocks in the device. figure 42. power_down_cfg 7 6 5 4 3 2 1 0 0 0 pd_refby2 0 pd_adcb 0 pd_adca pd_ref r-0b r-0b r/w-0b r-0b r/w-0b r-0b r/w-0b r/w-0b table 12. power_down_cfg field descriptions bit field type reset description 7-6 reserved r 00b reserved bits. do not write. reads return 00b. 5 pd_refby2 r/w 0b this bit powers down the refby2 output. 0: refby2 is not powered down 1: refby2 is powered down 4 reserved r 0b reserved bits. do not write. reads return 00b. 3 pd_adcb r/w 0b this bit powers down the adc_b and refbuf_b. 0: adc_b and refbuf_b are not powered down 1: adc_b and refbuf_b are powered down 2 reserved r 0b reserved bits. do not write. reads return 00b. 1 pd_adca r/w 0b this bit powers down the adc_a and refbuf_a. 0: adc_a and refbuf_a are not powered down 1: adc_a and refbuf_a are powered down 0 pd_ref r/w 0b this bit powers down the internal reference voltage. 0: internal reference voltage is not powered down 1: internal reference voltage is powered down advance information
36 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7.3 protocol_cfg register (address = 2h) [reset = 00h] this register configures the clock polarity (cpol), clock phase (cpha) for data transfer, and sets the protocol for reading data from the device. figure 43. protocol_cfg 7 6 5 4 3 2 1 0 0 sdo_protocol 0 0 spi_cpol spi_cpha r-0b r/w-0b r-0b r-0b r/w-0b r/w-0b table 13. protocol_cfg field descriptions bit field type reset description 7 reserved r 0b reserved bits. do not write. reads return 0b. 6-4 sdo_protocol r/w 000b these bits set the protocol for reading data from the device. 000: legacy, spi-compatible protocols (spi-xy-s-sdr); spi- compatible protocols with bus width options and sdr (spi-xy-d- sdr and spi-xy-q-sdr) protocols 001: spi-compatible protocols with bus width options and ddr (spi-x1-s-ddr, spi-x1-d-ddr,spi-x1-q-ddr) protocols 010: clock re-timer (crt) protocols with sdr (crt-s-sdr, crt-d-sdr, crt-q-sdr) 011: crt protocols with ddr (crt-s-ddr, crt-d-ddr, crt- q-ddr) 1xx: parallel byte protocols. 3-2 reserved r 00b reserved bits. do not write. reads return 00b. 1 spi_cpol r/w 0b this bit sets the clock polarity for reading data from the device and writing data into the device. 0: cpol = 0 1: cpol = 1 0 spi_cpha r/w 0b this bit sets the clock phase for reading data from the device and writing data into the device. 0: cpha = 0 1: cpha = 1 7.7.4 bus_width register (address = 3h) [reset = 00h] this register configures the bus width (number of sdo lines) for reading data from the device. figure 44. bus_width 7 6 5 4 3 2 1 0 0 0 0 0 0 0 sdo_width r-0b r-0b r-0b r-0b r-0b r-0b r/w-00b table 14. bus_width field descriptions bit field type reset description 7-2 reserved r 000000b reserved bits. do not write. reads return 000000b. 1-0 sdo_width r/w 00b these bits set the number of sdo lines for reading data from the device. 0x: one sdo per adc 10: dual sdo per adc 11: quad sdo per adc if the device is configured for parallel byte protocol, then sdo_width is ignored and the device sends data over all eight sdo lines as per the parallel byte protocol. advance information
37 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7.5 crt_cfg register (address = 4h) [reset = 00h] this register selects the clock source for the strobe output for clock re-timer (crt) protocols. figure 45. crt_cfg 7 6 5 4 3 2 1 0 0 0 0 0 0 0 crt_clk_select r-0b r-0b r-0b r-0b r-0b r-0b r/w-00b table 15. crt_cfg field descriptions bit field type reset description 7-2 reserved r 000000b reserved bits. do not write. reads return 000000b. 1-0 crt_clk_select r/w 00b these bits select the clock source for the strobe output for crt protocols. 00: sclk is used for the strobe output 01: intclk is used for the strobe output 10: intclk/2 is used for the strobe output 11: intclk/4 is used for the strobe output intclk is generated from the internal oscillator of the device. 7.7.6 output_data_word_cfg register (address = 5h) [reset = 00h] this register configures the alignment of output data word, sets the output data word to a fixed pattern, and selects the format for the output data word in the parallel byte protocol. figure 46. output_data_word_cfg 7 6 5 4 3 2 1 0 0 0 ready_mask parallel_mode_ data_format 0 0 fixed_pattern_ data data_right_ aligned r-0b r-0b r/w-0b r-0b r-0b r-0b r/w-0b r/w-0b table 16. output_data_word_cfg field descriptions bit field type reset description 7-6 reserved r 00b reserved bits. do not write. reads return 00b. 5 ready_mask r/w 0b this bit masks the ready output. 0: does not mask the ready output 1: masks the ready output, ready is set to 0 the strobe output is provided in crt protocols even if ready_mask is set to 1. ti recommends masking the ready output for the conversion control and data transfer frame with wide read cycle (zone 2 transfer) section. 4 parallel_mode_data_format r/w 0b this bit selects the format for the output data word in the parallel byte protocol. 0: data format aa: byte from adc_a followed by byte from adc_a (pb-xy-aa-zdr protocols) 1: data format ab: byte from adc_a followed by byte from adc_b (pb-xy-ab-zdr protocols) 3-2 reserved r 00b reserved bits. do not write. reads return 00b. 1 fixed_pattern_data r/w 0b this bit enables a fixed pattern in the output data word. 0: device provides the conversion results from the register data in the output data word 1: device provides a fixed pattern (a55aa55ah) in the output data word 0 data_right_aligned r/w 0b this bit enables the right alignment in the output data word for ads9234 r devices. 0: data are left-aligned in the output data word 1: data are right-aligned in the output data word advance information
38 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7.7 data_avg_cfg register (address = 6h) [reset = 00h] this register configures the averaging of conversion results. figure 47. data_avg_cfg 7 6 5 4 3 2 1 0 0 0 0 0 0 0 en_data_avg r-0b r-0b r-0b r-0b r-0b r-0b r/w-00b table 17. data_avg_cfg field descriptions bit field type reset description 7-2 reserved r 000000b reserved bits. do not write. reads return 000000b. 1-0 en_data_avg r/w 00b these bits enable averaging of conversion results. 0x: no averaging 10: enables averaging of two conversion results 11: enables averaging of four conversion results 7.7.8 refby2_offset (address = 7h) [reset = 00h] this register enables the offset for the refby2 output. figure 48. refby2_offset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 en_refby2_offset r-0b r-0b r-0b r-0b r-0b r-0b r-0b r/w-00b table 18. refby2_offset field descriptions bit field type reset description 7-1 reserved r 0000000b reserved bits. do not write. reads return 000000b. 0 en_refby2_offset r/w 0b this bit enables the offset for the refby2 output. 0: offset for the refby2 output is disabled 1: offset for the refby2 output is enabled and the refby2 output increases by 100 mv advance information
39 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the two primary circuits required to maximize the performance of a high-precision, successive approximation register (sar) analog-to-digital converter (adc) are the input driver and the reference driver circuits. this section presents general principles for designing these circuits, followed by an application circuit designed using the ads92x4r. 8.1.1 adc input driver the input driver circuit for a high-precision adc mainly consists of two parts: a driving amplifier and a charge kickback filter. the amplifier is used for signal conditioning of the input signal and the low output impedance of the amplifier provides a buffer between the signal source and the switched capacitor inputs of the adc. the charge kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the adc, and band-limits the wideband noise contributed by the front-end circuit. careful design of the front-end circuit is critical to meet the linearity and noise performance of the ads92x4r. 8.1.1.1 charge-kickback filter the charge-kickback filter is an rc filter at the input pins of the adc that filters the broadband noise from the front-end drive circuitry, and attenuates the sampling charge injection from the switched-capacitor input stage of the adc. a filter capacitor, c flt (as shown in figure 49 ), is connected from each input pin of the adc to the ground. this capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. generally, the value of this capacitor must be at least 20 times the specified value of the adc sampling capacitance. for the ads92x4r, the input sampling capacitance is equal to 16 pf; therefore, for optimal performance, keep c flt greater than 320 pf. this capacitor must be a cog- or npo-type. the type of dielectric used in cog or npo ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. figure 49. charge kickback filter driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier marginally unstable. to avoid amplifier stability issues, series isolation resistors (r flt ) are used at the output of the amplifiers. a higher value of r flt helps with amplifier stability, but adds distortion as a result of interactions with the nonlinear input impedance of the adc. distortion increases with source impedance, input signal frequency, and input signal amplitude. therefore, the selection of r flt requires balancing the stability of the driver amplifier and distortion performance of the design. always verify the stability and settling behavior of the driving amplifier and charge-kickback filter by tina-ti ? spice simulation. keep the tolerance of the selected resistors less than 1% to keep the inputs balanced. device r flt r flt c flt c flt advance information
40 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.2 input amplifier selection selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance goals, of the data acquisition system. some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the adc are: ? small-signal bandwidth. select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the adc sample-and-hold capacitor and the rc filter (the charge-kickback filter) at the inputs of the adc. higher bandwidth amplifiers offer faster settling times when driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at higher input frequencies. equation 4 describes the unity gain bandwidth (ugb) of the amplifier to be selected in order to maintain the overall stability of the input driver circuit: (4) ? distortion. both the adc and the input driver introduce distortion in a data acquisition block. equation 5 shows that to make sure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 db less than the distortion of the adc: (5) ? noise. noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in snr performance of the system. generally, to make sure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the adc. equation 6 explains that noise from the input driver circuit is band-limited by designing a low cutoff frequency, charge-kickback filte: where ? v 1 / f_amp_pp is the peak-to-peak flicker noise in v ? e n_rms is the amplifier broadband noise density in nv/ hz ? f ? 3db is the 3-db bandwidth of the charge-kickback filter ? n g is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration (6) ? settling time. for dc signals with fast transients that are common in a multiplexed application, the input signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. this condition is critical to maintain the overall linearity performance of the adc. typically, amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit accuracy. therefore, always verify the settling behavior of the input driver by tina-ti spice simulations before selecting the amplifier. flt flt 1 ugb 4 2 r c s t u ? u u ? 1 ? 1 ? u u d u s u ? ? ? 1 ? u u 20 db snr ref db3 2 rms _n 2 pp_ amp _ f 1 g 10 2 v 5 1 f 2 e 6.6 v 2 n db 10 thd thd adc amp d advance information
41 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 typical application figure 50. daq circuit for lowest distortion and noise with the ads92x4r for a 100-khz input signal 8.2.1 design requirements the design parameters are listed in table 19 for this example. table 19. design parameters design parameter example value adc sample rate 3 msps analog input signal 100 khz, 8.192 v pp , fully differential snr > 92 db thd < ? 105db inl < 1 lsb power supply 5-v analog, 3.3-v digital 8.2.2 detailed design procedure figure 50 shows an application circuit for this example. the device incorporates an internal 2.5-v reference voltage and independent matched reference buffers for each adc. the internal reference output (refout) is decoupled with a 1- f capacitor. the matched reference buffers provide a gain of 1.6384 v/v and generate a high-precision, 4.096-v reference voltage for each adc channel. decouple the reference buffer outputs (the refp_a and refp_b pins) with the refm_a and refm_b pins, respectively, with 10- f decoupling capacitors. the circuit in figure 50 shows a fully-differential data acquisition (daq) block optimized for low distortion and noise using the ths4551 and the ads92x4r. both differential adc inputs are driven using a high- bandwidth, low-distortion, fully differential amplifier (fda) designed in a gain of 1 v/v and an optimal rc charge- adc_a adc_b refout serial interface refbuf_b refbuf_a internal v ref internal v ref gnd avdd 1 f 1 f 12 29 30 11 1 k 1 k 1 k 1 k 4 4 3300 pf + + - - 1 k 1 k 4 4 3300 pf + + - - 330pf 330pf 330pf 330pf 1 k 1 k ths4551 ths4551 10 f refp_a refp_m 10 f refp_b refm_b 31 32 10 9 1 f 5 4 ainp_a ainm_a ainm_b ainp_b 1 2 78 v ocm v ocm refby2 3 4 gnd 1 f gnd gnd avdd avdd gnd gnd gnd gnd gnd 1 f 28 27 gnd dvdd ads92x4r refby2 refby2 refby2 advance information
42 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated kickback filter before going to the adc. generally, the distortion from the input driver must be at least 10 db less than the adc distortion. therefore, these circuits use the low-power ths4551 as an input driver that provides exceptional ac performance because of its extremely low-distortion and high bandwidth specifications. in addition, the components of the charge kickback filter are selected to keep the noise from the front-end circuit low without adding distortion. this front-end circuit configuration requires a differential signal at the input of the fda and provides a differential output to drive the adc inputs. the fda establishes a fixed common-mode voltage at the adc inputs using the vocm input pin from the fda. the ads92x4r incorporates a refby2 buffer output for setting the common-mode voltage. the ads92x4r refby2 output is decoupled using a 1- f capacitor and connected to each fda vocm input pin. each vocm pin is decoupled using a 0.1- f capacitor. for a complete schematic, see the ADS9224Revm-pdk user ' s guide located in the ADS9224R sar analog to digital converter evaluation module tool folder . 8.2.3 application curves figure 51 provides the typical fft for the circuit in figure 50 and figure 52 provides the typical inl for the circuit in figure 50 . snr = 92.8 db, thd = ? 105 db, enob = 14.9 bits figure 51. typical fft with 100-khz signal inl = 0.8 lsb, dnl = 0.2 lsb figure 52. typical inl frequency(hz) signal power(db) 0 200000 400000 600000 800000 1000000 -180 -150 -120 -90 -60 -30 0 d001 output code inl(lsb) -35000 -25000 -15000 -5000 5000 15000 25000 35000 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 d002 advance information
43 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the devices have two separate power supplies: avdd and dvdd. the reference buffers, internal reference voltage, and converter modules (adc_a and adc_b) operate on avdd. the serial interface operates on dvdd. avdd and dvdd can be independently set to any value within their permissible ranges. to operate the device with sclk more than 20-mhz, ti recommends to set the dvdd voltage as: 2.35 v dvdd 5.5 v. as shown in figure 53 , connect pins 12 and 29 together and place 1- f decoupling capacitors between pin 12 (avdd) and pin11 (gnd), and between pin 29 (avdd) and pin 30 (gnd). to decouple the dvdd supply, place a 1- f decoupling capacitor between pin 28 (dvdd) and pin 27 (gnd). . figure 53. power-supply decoupling advance information ainp_a dvdd ainm_a adc_a ainp_b ainm_b adc_b gnd avdd gnd serial interface refbuf_b refbuf_a avdd avdd avdd internal v ref internal v ref avdd gnd avdd avdd 1 f 1 f 1 f 12 29 30 11 28 27
44 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines this section provides some layout guidelines for achieving optimum performance with the ads92x4r. 10.1.1 signal path as illustrated in figure 54 , the analog input signals are routed in opposite directions to the digital connections. the reference decoupling components are kept away from the switching digital signals. this arrangement prevents noise generated by digital switching activity from coupling to sensitive analog signals. 10.1.2 grounding and pcb stack-up low inductance grounding is critical for achieving optimum performance. grounding inductance is kept below 1 nh with 15-mil grounding vias and a printed circuit board (pcb) layout design that has at least four layers. place all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner layers to minimize via length to ground. 10.1.3 decoupling of power supplies place the decoupling capacitors on avdd and dvdd within 20 mil from the respective pins, and use a 15-mil via to ground from each capacitor. avoid placing vias between any supply pin and the respective decoupling capacitor. 10.1.4 reference decoupling dynamic currents are present at the refp_x and refm_x pins during the conversion phase, and excellent decoupling is required to achieve optimum performance. place a 10- f, x7r-grade, ceramic capacitor with at least a 10-v rating, as illustrated in figure 54 . select 0603- or 0805-size capacitors to keep equivalent series inductance (esl) low. connect the refm_x pins to the decoupling capacitor before a ground via. also place decoupling capacitors on the refout and refby2 pins. 10.1.5 differential input decoupling dynamic currents are also present at the differential analog inputs of the ads92x4r. use c0g- or npo-type capacitors to decouple these inputs because with these type of capacitors, capacitance stays almost constant over the full input voltage range. lower-quality capacitors (such as x5r and x7r) have large capacitance changes over the full input-voltage range that may cause degradation in the performance of the device. advance information
45 ADS9224R www.ti.com sbas876 ? august 2018 product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example note: dimensions are in cm. figure 54. example layout for the ads92x4r advance information ads92x4 c refout c refby2 c diff_b c flt_b_2 r flt_b_2 c flt_b_1 r flt_b_1 c flt_a_1 c flt_a_2 c diff_a r flt_a_1 r flt_a_2 c refp_a c refp_b c avdd c avdd c dvdd 1 8 9 16 17 24 25 32
46 ADS9224R sbas876 ? august 2018 www.ti.com product folder links: ADS9224R submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 related documentation for related documentation see the following: ? ths4551 low-noise, precision, 150-mhz, fully differential amplifier ? ti precision designs: verified design 12 bit 1 msps single supply dual channel data acquisition system for optical encoders in motor control application ? ref50xx low-noise, very low drift, precision voltage reference ? opax350 high-speed, single-supply, rail-to-rail operational amplifiers microamplifier series ? ths452x very low power, negative rail input, rail-to-rail output, fully differential amplifier ? ADS9224Revm-pdk user ' s guide 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks tina-ti, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 24-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ADS9224Rirhbr preview vqfn rhb 32 3000 tbd call ti call ti -40 to 125 xds9224rirhbr active vqfn rhb 32 3000 tbd call ti call ti -40 to 125 xds9234rirhbr active vqfn rhb 32 3000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 24-aug-2018 addendum-page 2

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